Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for forming fine patterns of a semiconductor device.
As semiconductor devices become highly integrated, the line widths of patterns become narrower. However, with conventional photoresist technologies, it has become difficult to form patterns for semiconductor devices using under 40 nm process due to limitations in resolution of exposure equipment.
To address this concern, a Double Patterning Technology (DPT) process and a Spacer Patterning Technology (SPT) process may be used. The DPT process includes a Double Exposure Etch Technology (DE2T) process and a process of exposing a pattern having a period twice as wide as a target pattern period and performing an etch process.
The DE2T process may be relatively complicated due to additional processes performed with use of two masks, and the DE2T process raises a concern in that a pattern may not be properly formed when misalignment occurs between the two masks.
Thus, use of the SPT process is often desirable. Since the SPT process uses a mask process for patterning once, a concern with respect to misalignment between masks may be alleviated.
However, in using the SPT process, a process for cutting a line pattern and a process for patterning a peripheral region are used to form an isolation layer pattern that define active regions, where additional masks and additional etch and deposition processes using the additional masks are often performed.
The additional masks often add significant costs and decrease productivity in a semiconductor device fabrication process.
Therefore, a method for simplifying the SPT process to reduce production costs and increase productivity may be useful.